A high-performance 128-to-1 CMOS multiplexer tree

Abstract

A high-performance 128-input CMOS multiplexer (MUX) tree is designed in this study. In order to enhance the speed, the high-speed feature of traditional transmission-gate MUX circuits and CMOS MUX circuits are integrated to the 128-to-1 MUX tree with high transmission speed. The circuit simulation in the CMOS 0.18μm process presents 26% reduction of delay time, comparing to the 128-to-1 MUX tree composed of traditional 2-to-1 CMOS.