A 0.11mm/sup 2/ low-power A/D-converter cell for 10b 10MS/s operation

Abstract

A 10 bit 10 MS/s cyclic analog-to-digital converter has been implemented using 0.18 /spl mu/m CMOS technology. The converter was optimized with respect to area and power consumption in order to allow the integration of a multichannel array within a complex logic chip. The power consumption is 9.5 mW. The area per A/D-converter cell is 0.11 mm/sup 2/. The proposed cyclic converter architecture together with some implementation aspects, like working with one amplifier only and reusing the signal capacitors for the common-mode feedback helped to meet the requirements of the application.