Detection of gate-oxide defects with timing tests at reduced power supply

Abstract

In this paper, we focus on the detection of small gate-oxide defects, which can escape production tests but lead to early-life-failures (ELF) during normal operation. Very-Low-Voltage (VLV) and MinVDD testing have been proposed in the past to screen such “weak” ICs. However, small defects that are not severe enough to trigger logic failures can still escape such tests given the fact that power supply voltage cannot be arbitrarily lowered in a given technology. We suggest a novel approach for increasing the sensitivity of detection of these small gate-oxide defects by applying timing tests in a reduced power supply environment. While not severe enough to cause logic failures, small oxide defects can still introduce observable anomalies in the timing of affected paths, which is amplified at reduced power supply voltages. Experimental simulation results using NanGate 45nm technology are provided to substantiate our conclusions.