A study on the correlation between experiment and simulation board level drop test for SSD

2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) Pub Date : 2017-04-03 DOI:10.1109/EUROSIME.2017.7926215

T. Kang, Yong Chang Lee, Byung Kwon Bae, Won Seob Song, Jae Sung Lee

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引用次数: 1

Abstract

Recently, handheld electronic products are prone to being dropped during their useful service life because of their size and weight. Board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. Therefore, board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this study, we examine and compare simulation the board level drop test of SSD. Applying the JEDEC (JESD22-B111) standard present a finite element modeling of the BGA package assembly was performed to study the stress and strain behavior of the solder joints during drop test. The simulation revealed that maximum stress was located at the outermost solder ball in the PCB or Package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

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固态硬盘仿真板跌落试验与实验的相关性研究

最近，手持式电子产品由于其体积和重量的原因，在其使用寿命期间很容易掉落。集成电路封装在跌落冲击下的板级焊点可靠性性能成为半导体和电子产品制造商非常关注的问题。封装容易受到焊点失效的影响，这是由PCB弯曲和冲击时的机械冲击共同引起的。因此，板面跌落测试是表征微型手持产品焊点可靠性的有效方法。在本研究中，我们对固态硬盘的板级跌落测试进行了模拟检验和比较。应用JEDEC (JESD22-B111)标准建立了BGA封装组件的有限元模型，研究了跌落试验过程中焊点的应力应变行为。模拟结果表明，最大应力位于PCB或封装侧最外层的焊球处，与跌落可靠性试验失效分析中观察到的裂纹起裂位置吻合较好。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)

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