An Efficient Approach to Design a Comparator for SAR-ADC

Abstract

In modern expertise inventions the essential growth has been observed in electronic sectors. All the electronic devices work on the signals that can be either analog or digital. With the advancement in CMOS technologies, IC’s were designed that can be used in electronic systems, where the major concern was power consumption without affecting the performance of the device. One of the vital blocks in this system is analog-digital converter (ADC) that acts as interface amid the analog worlds to the digital world. Among the prevailing ADC architectures, one of the utmost used is successive approximation register. SAR based ADC achieves an improved sampling rate at low power and high speed. It is appropriate for data acquisition and provides a worthy trade-off amongst design complexity and power dissipation by providing high-energy efficiency. In SAR-ADC architectures, one of the vital blocks that consume much amount of power is comparator. This paper converses the design of comparator simulated at 90nm and 45nm CMOS technology that has reduced the overall power consumption of SAR-ADC. Finally, it concludes the appropriate method that can be utilized to accomplish ultra-low power consumption and can be used for all electronic implant devices without affecting the performance of SAR-ADC.