Better bottom line through lower component stress

Abstract

This paper discusses the value of having a methodology and capability to de-risk the design from stress de-rating point of view and how to improve the bottom line by following and building enough margins in the design. As designs are becoming more complex and development time is getting shorter, the chance of designing overstressed components and introducing schematic connectivity errors increases significantly which could lead to higher number of failures. This scenario is a one of typical cases where the overall product bottom line is impacted. Electronic assemblies are utilizing complex circuitry with smarter and denser ICs with more than 1000 pins. Due to sophisticated features and requirements of new designs, power dissipation and temperatures are increasing that jeopardizes the design reliability and integrity for mission critical systems. In addition to lack of acceptable product performance, mission critical and non-critical products will experience higher number of returns where it directly impacts customer confidence and cost of ownership. The challenge for today's reliability and design engineers is to perform an analysis in a timely manner at the schematic level before the first prototype to identify overstressed components and pins to prevent hardware re-spin. The intent if this paper is to demonstrate methods that should be implemented during the design phase of electronic boards, which will help the designer and the reliability analyst to detect components with high operational stress. The stress level can be power, voltage, current or temperature. Through this technique, product time to market will be reduced and decreases the risk of hardware failures during product operation. The analysis will provide best rules for schematic modeling, stress analysis and the importance of de-rating standard in a design. The paper will include the results of more than 20 analysis performed utilizing the recommended best practices and how many re-spins were prevented. This analysis can be performed on any types of components such as analog, digital and RF.