A 7nm CMOS technology platform for mobile and high performance compute application

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI:10.1109/IEDM.2017.8268476

S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan, M. Eller, Y. Fan, Q. Fang, A. Gassaria, R. Gauthier, S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han, M. Hasan, J. Higman, J. Holt, L. Hu, L. Huang, C. Huang, T. Hung, Y. Jin, J. Johnson, S. Johnson, V. Joshi, M. Joshi, P. Justison, S. Kalaga, T. Kim, W. Kim, R. Krishnan, B. Krishnan, K. Anil, M. Kumar, J. Lee, R. Lee, J. Lemon, S. L. Liew, P. Lindo, M. Lingalugari, M. Lipinski, P. Liu, J. Liu, S. Lucarini, W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski, J.

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引用次数: 44

Abstract

We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.

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7nm CMOS技术平台，用于移动和高性能计算应用

我们提出了一个完全集成的7nm CMOS平台，具有第三代finFET架构，用于fin形成的SAQP和用于BEOL金属化的SADP。该技术比[1-3]中描述的14nm参考技术提高了2.8倍的路由逻辑密度和>40%的性能。通过独特的多工作功能流程，在片上启用了全系列的Vts。这可以同时实现出色的低压SRAM响应和高度缩放的存储区域。HD 6-T位单元大小为0.0269um2。这项7nm技术完全由浸没式光刻和先进的光学图形技术(如SAQP和SADP)实现。然而，该技术平台也被设计为利用EUV插入特定的多模式(MP)水平，以获得周期时间效益和制造效率。在这个先进的CMOS平台中，可以使用一套完整的基础和复杂的IP，以实现高性能计算(HPC)和移动应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2017 IEEE International Electron Devices Meeting (IEDM)

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