Optimizing RC tree delay in high speed ASICs through repeater insertion

Abstract

One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a global optimization algorithm for inserting repeaters into RC trees. The timing model predicts results generally within 10% of SPICE. The global optimization method exhibits total delay improvements of up to 86% over typical cascaded buffer insertion methods. The repeater timing model, global insertion methodology and algorithm, and software implementation are summarized in this paper.