Performance Evaluation of On-chip Interconnect System using Prospective Neural Network Design

Abstract

Due to technology scaling in deep submicron region, on-chip interconnects have become a major concerning issue for overall circuit performance. Therefore, it is necessary to evaluate the performance of interconnects in order to predict the output of design. In this paper, back-propagation feed forward neural network (FFNN) technique is employed for performance prediction of driver-interconnect-load (DIL) model. Levenberg-Marquardt (LM) algorithm is used as the training algorithm. The neural network model provides faster prediction when compared to the traditional performance analysis method. Also the proposed method works closely with the simulation methods thereby depicting the accuracy of the developed model. The dataset used for training of neural network (NN) is created using HSPICE. Performance parameters considered are delay and power dissipation. The several analyses are performed at 32nm technology.