Concurrent design analysis of A 8500V ESD-protected SP10T switch in SOI CMOS

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716560

X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph

引用次数: 0

Abstract

SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].

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SOI CMOS中8500V防静电SP10T开关并行设计分析

SPMT-ESD交互和协同设计分析是设计高ESD防护SPMT的关键。新的协同设计方法有助于在SOI CMOS中提供具有8500V ESD保护的高线性SP10T，与最先进的0-700V ESD保护相比[1-3]。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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