A cache architecture

Abstract

Caches are widely used in computers. This paper proposes an algorithm to increase the number of cache ways in w-way set associative cache to maximum of 2w ways. The addresses resulting in conflict miss to a set are placed in other_set. The other set is chosen as the set with maximum vacant cache ways. The least recently used cache way is replaced in case of no vacant cache ways in the other_set. An owner vector indicates a line to belong to a set. The proposed model is simulated using SPEC2K benchmarks. A performance improvement of 2.5% in average memory access time is observed over traditional set associative cache. The performance is comparable to 2w-way set associative cache for chosen parameters. The energy consumption implementing tag cache model showed an increase of about 13% over traditional set associative cache of same size.