Silicon thickness variation of FD-SOI wafers investigated by differential reflective microscopy

Abstract

Fully depleted silicon-on-insulator (FD-SOI) wafers with very thin Si top layers in the range of ten nanometers have to fulfill very strict uniformity requirements in the Å range across the wafer for the latest CMOS technologies based on 22nm technology. Hereby, the thickness variation of the complete Si layer defining the body thickness of the transistor and thus the device properties have to be determined at not only a few locations of the wafer but a full lateral characterization is desirable. We have used differential reflective microscopy (DRM) in low-resolution mode for full-wafer maps and high-resolution mode at discrete locations to characterize the SOI thickness variation. Full wafer maps with DRM provide higher resolution than ellipsometry and can be used to control SOI manufacturing processes. We compare SOI thickness variation obtained from high-resolution measurements to ITRS roadmap requirements.