Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC

Ben Keller, M. Cochet, B. Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, A. Puggelli, Stevo Bailey, P. Chiu, D. Dabbelt, Colin Schmidt, E. Alon, K. Asanović, B. Nikolić
{"title":"Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC","authors":"Ben Keller, M. Cochet, B. Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, A. Puggelli, Stevo Bailey, P. Chiu, D. Dabbelt, Colin Schmidt, E. Alon, K. Asanović, B. Nikolić","doi":"10.1109/ESSCIRC.2016.7598294","DOIUrl":null,"url":null,"abstract":"This work presents a RISC-V system-on-chip (SoC) with integrated voltage regulation and power management implemented in 28nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82-89% system conversion efficiency across a wide operating range, yielding a total system efficiency of 41.8 double-precision GFLOPS/W. Measurement circuits can detect changes in processor workload and an integrated power management unit responds by adjusting the core voltage at sub-microsecond timescales. The power management system reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty and 2.0% area overhead, enabling extremely fine-grained (<;1μs) adaptive voltage scaling for mobile devices.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

Abstract

This work presents a RISC-V system-on-chip (SoC) with integrated voltage regulation and power management implemented in 28nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82-89% system conversion efficiency across a wide operating range, yielding a total system efficiency of 41.8 double-precision GFLOPS/W. Measurement circuits can detect changes in processor workload and an integrated power management unit responds by adjusting the core voltage at sub-microsecond timescales. The power management system reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty and 2.0% area overhead, enabling extremely fine-grained (<;1μs) adaptive voltage scaling for mobile devices.
28nm FD-SOI处理器SoC的亚微秒自适应电压缩放
这项工作提出了一个集成电压调节和电源管理的RISC-V片上系统(SoC),在28nm FD-SOI中实现。一个完全集成的开关电容DC-DC转换器,加上一个自适应时钟系统,在宽工作范围内实现82-89%的系统转换效率,产生41.8双精度GFLOPS/W的总系统效率。测量电路可以检测处理器工作负载的变化,集成电源管理单元通过在亚微秒时间尺度上调整核心电压来响应。该电源管理系统将合成基准测试的能耗降低了39.8%,性能损失可以忽略不计,面积开销为2.0%,为移动设备提供了极细粒度(<;1μs)的自适应电压缩放。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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