A Multithreaded Soft Processor for SoPC Area Reduction

B. Fort, D. Capalija, Z. Vranesic, S. Brown
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引用次数: 75

Abstract

The growth in size and performance of field programmable gate arrays (FPGAs) has compelled system-on-a-programmable-chip (SoPC) designers to use soft processors for controlling systems with large numbers of intellectual property (IP) blocks. Soft processors control IP blocks, which are accessed by the processor either as peripheral devices or/and by using custom instructions (CIs). In large systems, chip multiprocessors (CMPs) are used to execute many programs concurrently. When these programs require the use of the same IP blocks which are accessed as peripheral devices, they may have to stall waiting for their turn. In the case of CIs, the FPGA logic blocks that implement the CIs may have to be replicated for each processor. In both of these cases FPGA area is wasted, either by idle soft processors or the replication of CI logic blocks. This paper presents a multithreaded (MT) soft processor for area reduction in SoPC implementations. An MT processor allows multiple programs to access the same IP without the need for the logic replication or the replication of whole processors. We first designed a single-threaded processor that is instruction-set compatible to Altera's Nios II soft processor. Our processor is approximately the same size as the Nios II economy version, with equivalent performance. We augmented our processor to have 4-way interleaved multithreading capabilities. This paper compares the area usage and performance of the MT processor versus two CMP systems, using Altera's and our single-threaded processors, separately. Our results show that we can achieve an area savings of about 45% for the processor itself, in addition to the area savings due to not replicating CI logic blocks
一种用于SoPC面积缩减的多线程软处理器
现场可编程门阵列(fpga)的尺寸和性能的增长迫使系统单可编程芯片(SoPC)设计人员使用软处理器来控制具有大量知识产权(IP)块的系统。软处理器控制IP块,处理器可以将其作为外围设备或/或使用自定义指令(ci)访问IP块。在大型系统中,芯片多处理器(cmp)用于并发执行多个程序。当这些程序需要使用作为外围设备访问的相同IP块时,它们可能不得不停止等待轮到它们。在ci的情况下,实现ci的FPGA逻辑块可能必须为每个处理器复制。在这两种情况下,FPGA区域都被浪费了,要么是空闲的软处理器,要么是CI逻辑块的复制。本文提出了一种用于SoPC实现中面积缩减的多线程(MT)软处理器。MT处理器允许多个程序访问同一个IP,而不需要逻辑复制或整个处理器的复制。我们首先设计了一个指令集与Altera的Nios II软处理器兼容的单线程处理器。我们的处理器大小与Nios II经济型差不多,但性能相当。我们增强了处理器,使其具有4路交错多线程功能。本文分别使用Altera和我们的单线程处理器,比较了MT处理器与两种CMP系统的面积使用和性能。我们的结果表明,除了由于不复制CI逻辑块而节省的面积外,我们还可以为处理器本身节省约45%的面积
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