Design of a continuous fractional frequency divider in 0.35μm CMOS process

Abstract

This work introduces a new and simple architecture for fractional frequency dividers in order to reduce the jitter in frequency synthesizers. The major advantage of the proposed architecture is that unlike the conventional fractional frequency divider, it does not need the periodic change of the division ratio. Therefore, the fractional division is continuous. Also, the new divider simplifies loop characteristics of the synthesizer and decreases the lock time. The division ratio varies from 1.125 to 10 and the step size of the fractional frequency divider is equal to 1/8. Post-layout simulation results using HSPICE for CSMC 0.35μm technology depict the low jitter behavior of the designed system.