A current testing for CMOS logic circuits applying random patterns and monitoring dynamic power supply current

Abstract

Assuming a stuck-at fault and stuck-open fault, the authors discussed a random current testing for CMOS logic circuits by monitoring a dynamic power supply current. Random patterns are generated using a modified LFSR, where the outputs of a CUT are fed back to an LFSR. This modification is intended for amplifying the influence of a fault near a primary outputs on the dynamic current. Simulation results showed that the modified LFSR works well for detectability, and a high fault coverage can be obtained applying a small number of test vectors.<>