Alejandro Campos-Cruz, E. Tlelo-Cuautle, G. E. Flores-Verdad
{"title":"Review: Advances in BTI modeling for the design of reliable ICs","authors":"Alejandro Campos-Cruz, E. Tlelo-Cuautle, G. E. Flores-Verdad","doi":"10.1109/ICEEE.2016.7751211","DOIUrl":null,"url":null,"abstract":"A brief review of the impact of Bias-Temperature Instability (BTI) on Integrated Circuits (IC) is presented. The importance of this problem with the performance degradation on commercial IC designs, such as Physical Unclonable Functions (PUF) and Ring Oscillator (RO), which are key elements on security applications, is emphasized. A physical interpretation of this phenomenon is provided along with a brief description of the model's evolution, commonly used to simulate the degradation of transistor's parameters at high temperature and voltage supply conditions. Finally, some reported techniques are described to accomplish a better IC design, from the Process, Temperature and Voltage (PVT) variations point of view, lifetime yield optimization and weak spot detection on circuit's architecture.","PeriodicalId":285464,"journal":{"name":"2016 13th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 13th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEE.2016.7751211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A brief review of the impact of Bias-Temperature Instability (BTI) on Integrated Circuits (IC) is presented. The importance of this problem with the performance degradation on commercial IC designs, such as Physical Unclonable Functions (PUF) and Ring Oscillator (RO), which are key elements on security applications, is emphasized. A physical interpretation of this phenomenon is provided along with a brief description of the model's evolution, commonly used to simulate the degradation of transistor's parameters at high temperature and voltage supply conditions. Finally, some reported techniques are described to accomplish a better IC design, from the Process, Temperature and Voltage (PVT) variations point of view, lifetime yield optimization and weak spot detection on circuit's architecture.