Design of ESD protections for ECG applications

Abstract

This paper presents the design of Electrostatic Discharge (ESD) protections for a remote Electroencephalograph (ECG). Design and layout guidelines are analyzed to improve the ESD robustness of a Grounded-Gate NMOS (GGNMOS) cell based on a single well CMOS-only process. Experimental validation is done by means of a Time Domain Reflectometry (TDR) technique known as Transmission Line Pulse (TLP) testing. The silicon implementation of the proposed design passes ±3700V in the Human-Body Model (HBM).