Buck converter modeling in SystemVerilog for verification and virtual test applications

Abstract

Functional verification and Virtual Test, which is verification of a test procedure, of mixed-signal circuits share the need for efficient simulation capabilities. Switching DC/DC converters are a particularly hard problem, because traditional SPICE-type simulation approaches incur simulation efforts which prevent one from covering all conceivable use-cases. The new IEEE 1800-2012 standard for SystemVerilog (SV) introduces the concepts of user-defined data types (UDT) and user defined resolution functions (UDR) which allows for easier modeling of the loading effects. Such improvementes together with the high performance of an event-driven simulator increase the capability of SystemVerilog in supporting efficient, fast to simulate and yet accurate models of mixed-signal circuits. In this contribution, we propose a block-level modeling strategy which considers the loading effects caused by either subsequent blocks in the signal path or by faults assumed in the circuit.