Design and implementation of a 9-bit 8MHz DPWM with AMI06 process

Abstract

This paper presents one solution to a question what is the maximum switching frequency of a hybrid digital pulse width modulator (DPWM) if semiconductor process is given and resolution bit number is set high. This paper also proposes a hybrid DPWM structure where voltage controlled oscillator (VCO) and delay line are separated so as to enhance design flexibility and decrease power consumption. And, a phase locked loop is included in the DPWM providing wide-frequency range signal synchronization as well as process, voltage and temperature (PVT) insensitivity facilitating accurate switching frequency control. Taking low cost two metal layers 0.6¿m AMI06 process and 9-bits resolution bit requirement as an example, a 8MHz switching frequency DPWM is designed and implemented in 0.703mm2 die via MOSIS educational program. Chip test result showed that the maximal switching frequency approaches 7.4MHz when DPWM performance is guaranteed, the power consumption is 144¿A/MHzand the synchronization switching frequency range is from 1.8MHz to 7.4MHz.