A CAD Approach for Accurate Decap Estimation and Allocation for Supply Noise Reduction in SoC

Abstract

This article presents accurate decoupling capacitance (decap) estimation which are commonly used for suppression of power supply noise (PSN) in modern day system-on-chip (SoC). Supply noise is a major issue needs to be addressed for proper functioning which may lead to logic failure in digital integrated circuit. Capacitors directly effects the power consumption and delay parameters and hence the overall performance of integrated circuits. This article deals with flower pollination algorithm for decap estimation of supply noise reduction with a focus in improved performance of the integrated circuit. Also focus has been given for placement of decoupling capacitors. This work presents that supply noise has been reduced considerably with marginal increment in delay and power parameters. This CAD flow can also be used on any system-on-chip design.