Design, Reliability Investigation and Analysis of 60 GHz band LNA in 65nm CMOS for 5G Mobile Communication

Abstract

A LNA has been designed in Cadence simulator in 60 GHz band (57-64 GHz) in 65nm CMOS with microstrip as on-chip inductors. LNA has gain of 11.55 dB at 60 GHz. The noise figure is 4.98 dB at 60 GHz. The 3-dB bandwidth for this LNA design is 57-64 GHz. The stability factor (K) is greater than 1 for the entire range. Additionally, the 1-dB gain compression point (P1dB) is −10.0229 dBm and the IIP3 value is −2.2 dBm at 60 GHz. PVT (Process-Voltage-Temperature) simulations is also done for reliability investigation and analysis where the performance of LNA is tested under various process corners, temperatures and voltages. Gain of the amplifier was observed under different process corners, temperatures (from −40°C to 100°C) and voltages. It was observed that the amplifier’s gain was invariant in the voltage variation range of 1 - 1.4 V. Moreover, we observed that the higher peak in the gain graph is due to the fast-fast process corner parameter and the lower peak is due to the slow-slow process corner parameter. The highest peak gain was observed for the Fast-Fast process corner and at low temperature of −40°C and lowest peak gain for Slow-Slow process corner and at high temperature of 100°C. FoM (figure of merit) is 0.92 GHz/mW at 60 GHz. Hence a reliable design of LNA is achieved for the 60 GHz band for 5G mobile communication application.