Comparisons of bus transfer operations using PPS (pulsed power supply) and conventional CMOS in PWB and MCM environments

Abstract

A comparison of I/O power dissipation is compared for an adiabatic technique called PPS CMOS and conventional CMOS. The simulated results evaluated either a PWB or an MCM environment. A 32 bit bus with 8 loads on each bus is the model used for this paper. The results indicate that power and noise reductions are possible using PPS I/O buffers. Furthermore, the MCM is an optimum environment for the adiabatic logic family.