An x86 load/store unit with aggressive scheduling of load/store operations

Abstract

Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes crucial. We examine the scheduling policies of loads/stores on x86 superscalar microprocessors and propose a new aggressive scheduling policy called load speculation, which allows loads to precede the previous unsolved pending stores. Simulation results show that the load speculation achieves the higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the load speculation can achieve even higher performance.