A Novel Fault-Tolerant Last-Level Cache to Improve Reliability at Near-Threshold Voltage

W. Liu, Zhigang Wei, Wei Du
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引用次数: 1

Abstract

Near-threshold voltage computing (NTC) improves power and energy efficiency of cache by scaling transistor voltage. However, in large SRAM structures, such as last-level cache (LLC), a great number of bit-cell errors will occur when supply voltage scales to near-threshold voltage. In this paper, we propose a novel fault-tolerant LLC design (NFTLLC) to deal with a high failure rate which is higher than 1% at near-threshold voltage. NFTLLC corrects the single-error and compresses multi-error in Cache entry to improves the reliability of last-level cache. To validate the efficiency of NFTLLC, we implement NFTLLC and prior works in gem5, and simulate with SPEC CPU2006. The experiment shows that compared with Concertina when bit-cell failure rate is 1.1%, the performance of NFTLLC with 4-byte subblock size improves by 6.8% and the Cache capacity increases by 20.8%. Besides, miss rate decreases more than 53%, and overhead increases by 16.8% in minimum.
一种提高近阈值电压下可靠性的新型容错最后级缓存
近阈值电压计算(NTC)通过调节晶体管电压来提高高速缓存的功率和能量效率。然而,在大型SRAM结构中,如最后一级缓存(LLC),当电源电压扩展到接近阈值电压时,会发生大量的位元错误。在本文中,我们提出了一种新的容错LLC设计(NFTLLC)来处理在近阈值电压下高于1%的高故障率。NFTLLC通过纠正Cache表项中的单错误和压缩多错误,提高了最后一级Cache的可靠性。为了验证NFTLLC的有效性,我们在gem5中实现了NFTLLC和之前的工作,并在SPEC CPU2006中进行了仿真。实验表明,与位元故障率为1.1%的Concertina相比,4字节子块大小的NFTLLC的性能提高了6.8%,Cache容量提高了20.8%。脱靶率降低53%以上,费用最少增加16.8%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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