A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 /spl mu/m n-n gate CMOS technology

Abstract

A new channel engineering combined with optimization of channel epitaxy and suppression of TED (transient enhanced diffusion) is proposed for a practical 0.15 /spl mu/m n-n gate CMOS technology. An optimized channel profile with small Vth fluctuation provides an nMOS with no reverse short channel effect and a high performance BCpMOS.