Effect of tensile capping layer on 3-D stress profiles in FinFET channels

Abstract

Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator