Electromagnetic Compatibility in Leakage Current of CMOS Integrated Circuits

Zahra Abedi, S. Hemmady, T. Antonsen, E. Schamiloglu, P. Zarkesh-Ha
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引用次数: 2

Abstract

This paper presents an analytical model that predicts and characterizes the impact of Electromagnetic Interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the rate of increase in leakage current follows the modified Bessel function, which can be estimated using only a few primitive device parameters. Unlike other device and circuit parameters, leakage current is very sensitive to EMI, where only a few hundred millivolts of noise can increase the leakage current by a factor of 1000. The developed analytical model is successfully compared against measurement data from CMOS inverters fabricated using various TSMC’s standard CMOS processes, including 180 nm, 130 nm, and 65 nm. Based on the predictive model and experimental data, we show that the impact of EMI on the leakage current of CMOS integrated circuits is independent of technology scaling.
CMOS集成电路漏电流中的电磁兼容性
本文提出了一种预测和表征电磁干扰对CMOS集成电路漏电流影响的解析模型。结果表明,泄漏电流的增加速率遵循修正的贝塞尔函数,该函数可以只用几个基本的器件参数来估计。与其他器件和电路参数不同,泄漏电流对电磁干扰非常敏感,仅几百毫伏的噪声就能使泄漏电流增加1000倍。该分析模型成功地与采用台积电各种标准CMOS工艺(包括180 nm, 130 nm和65 nm)制造的CMOS逆变器的测量数据进行了比较。基于预测模型和实验数据,我们证明了电磁干扰对CMOS集成电路漏电流的影响与技术尺度无关。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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