Fuzzy-logic based low power solution for Network-on-Chip architectures

Abstract

Network-on-Chip (NoC) paradigm allows designers to integrate efficiently more intellectual properties (IPs) into a single chip system. However, the power consumption has become one of the most critical issues for designing such large complex systems. Low power design can be achieved by scaling the voltage and frequency of the target components. The question is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time while reducing as much as possible the power consumption. This paper presents a novel solution for NoC architectures to reduce power consumption using fuzzy-logic algorithms. As the communication traffic is not equally distributed over the network architecture, depending on the communication load, each router in the network will be applied with a corresponding voltage and frequency to minimize the power consumption while keeping necessary communication throughput.