X. Peng, A. Gao, Zheng Chen, Haosong Zhang, Yuefeng Li, Wenzhen Cao, Xiaoqiao Liu, H. Tang
{"title":"A Novel Comparator Offset Calibration Technique for SAR ADCs","authors":"X. Peng, A. Gao, Zheng Chen, Haosong Zhang, Yuefeng Li, Wenzhen Cao, Xiaoqiao Liu, H. Tang","doi":"10.1109/EDSSC.2018.8487062","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel comparator offset calibration technique for SAR ADCs. We realize the calibration in CDAC instead of the comparator circuit, so that the power consumption, area and circuit complexity barely increase, which is a big advantage compared to traditional ones. A 10-bit 100Msps SAR ADC applying our offset calibration is designed in a 55nm CMOS process. The post simulation results show that the ENOB achieves 9.5 bits and consumes a power of 4.4mW at the sampling rate of 100MHz.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2018.8487062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper proposes a novel comparator offset calibration technique for SAR ADCs. We realize the calibration in CDAC instead of the comparator circuit, so that the power consumption, area and circuit complexity barely increase, which is a big advantage compared to traditional ones. A 10-bit 100Msps SAR ADC applying our offset calibration is designed in a 55nm CMOS process. The post simulation results show that the ENOB achieves 9.5 bits and consumes a power of 4.4mW at the sampling rate of 100MHz.
提出了一种新的SAR adc比较器偏置校准技术。我们在CDAC中实现校准,而不是在比较器电路中,因此功耗、面积和电路复杂度几乎没有增加,与传统电路相比有很大的优势。采用55nm CMOS工艺设计了一个10位100Msps SAR ADC。后置仿真结果表明,在100MHz采样率下,ENOB达到9.5位,功耗为4.4mW。