A 1 V 6 b 50 MHz current-interpolating CMOS ADC

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797242

Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig

引用次数: 7

Abstract

A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.

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1 V 6 b 50 MHz电流插值CMOS ADC

采用电流插值技术实现了一个6 b 50 MHz的ADC，可在低至0.9 V的单个电池上工作，无需充电泵送。该原型芯片以0.35 /spl mu/m标准数字工艺制造，占地2.4 mm/spl × / 2mm，模拟电源和数字电源的功耗分别为10 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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