A 0.7–6 GHz low-voltage broadband folded mixer in 0.13-um CMOS

Abstract

This paper presents the design and analysis of a low-voltage down-conversion mixer in 0.13μm CMOS for 0.7-6 GHz applications. The proposed mixer is based on folded double-balanced Gilbert cell which is well-known for low voltage, simplicity and well-balanced performances. The folded topology allows the gm-stage and LO stage to have different currents. By setting the bias current in the PMOS switches near zero, the mixer DC offset due to device mismatch is greatly reduced. Capacitors are added parallel with the current generators to achieve the optimal IIP3 performance. Designed in SMIC 0.13-μm process, the mixer achieves a voltage gain (CG) of 5~7dB, a single-sideband noise figure (NF) of 11~13.2dB, and a third-order inter-modulation intercept point (IIP3) of 3.2~5dBm between 0.7~6GHz. The mixer core dissipates 5.8mW under 1.2 V supply.