{"title":"A Contrast and Motion-Sensitive Silicon Retina","authors":"A. Mhani, G. Bouvier, J. Hérault","doi":"10.1117/12.262517","DOIUrl":null,"url":null,"abstract":"This paper presents an analogue VLSI implementation of a model of retina. The retinal model includes the main synaptic interactions in the outer plexiform layer (OPL) of the vertebrate retina, namely the coupling between horizontals and cones cells. Using the signal processing tools, our model has been theoretically studied. Thereby the resulting chip is a contrast and motion-sensitive silicon retina with better signal-to-noise ratio. Analogue processing provides a continuous temporal processing, a low power dissipation, and height functionality. The chips has been fabricated in 1 ¿m CMOS technology, However the VLSI implementation is highly constraint by size.","PeriodicalId":333302,"journal":{"name":"ESSCIRC '95: Twenty-first European Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '95: Twenty-first European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.262517","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper presents an analogue VLSI implementation of a model of retina. The retinal model includes the main synaptic interactions in the outer plexiform layer (OPL) of the vertebrate retina, namely the coupling between horizontals and cones cells. Using the signal processing tools, our model has been theoretically studied. Thereby the resulting chip is a contrast and motion-sensitive silicon retina with better signal-to-noise ratio. Analogue processing provides a continuous temporal processing, a low power dissipation, and height functionality. The chips has been fabricated in 1 ¿m CMOS technology, However the VLSI implementation is highly constraint by size.