A visually oriented architectural fault simulation environment for WSI

Abstract

A visually oriented fault simulation environment for WSI architectures based on behavioral simulation of parallel message passing processors and switch-level fault simulation of selected processors is described. The environment was implemented by interfacing the CHAMP switch-level simulator with the OODRA behavioral simulator. The simulation environment was used to measure the fault coverage for a digital adaptive beamforming architecture with a synthetic workload. Fault coverage variation with input set size and array location was investigated. The rate at which faults produce errors in the architecture was also measured.<>