AE32000: an embedded microprocessor core

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896957

H.-C. Oh, H.-G. Kim, H.-S. Jung, J.-W. Lee, B. Kim, J. Jung, B.-G. Min, J.-Y. Lim, H. Lee, Kyeonghwan Kwon

引用次数: 3

Abstract

The ADC's EISC microprocessor family has been developed to address the need for reduction in the amount of memory access of today's embedded applications. In this paper, we introduce the microarchitecture of the AE32000 processor, a 32-bit member of the ADC's EISC family. Specifically, we discuss the pipelining scheme and LERI-instruction folding, and we present the performance of our current implementation. We also introduce a system implementation utilizing the AE32000 processor.

查看原文本刊更多论文

AE32000:嵌入式微处理器核心

ADC的EISC微处理器系列是为了满足当今嵌入式应用减少内存访问量的需求而开发的。在本文中，我们介绍了AE32000处理器的微结构，这是ADC的EISC家族的32位成员。具体来说，我们讨论了流水线方案和leri指令折叠，并给出了我们当前实现的性能。我们还介绍了一个利用AE32000处理器的系统实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

自引率

0.00%

发文量