K. Akarvardar, S. Cristoloveanu, P. Gentil, B. Blalock, B. Dufrene, M. Mojarradi
{"title":"Depletion-all-around in SOI G/sup 4/-FETs: a conduction mechanism with high performance","authors":"K. Akarvardar, S. Cristoloveanu, P. Gentil, B. Blalock, B. Dufrene, M. Mojarradi","doi":"10.1109/ESSDER.2004.1356528","DOIUrl":null,"url":null,"abstract":"Only in 4-gate SOI transistors (G/sup 4/-FETs) can the channel be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. The majority carriers flow in the film volume, far from interfaces and junctions. We show that inversion layers, formed at the front and back interface, enable the junction gates to have enhanced control on the volume channel. High performance is experimentally demonstrated in terms of transconductance, subthreshold swing and g/sub m//I/sub d/ ratio. The basic mechanism, which involves a specific 2D gate coupling, is explained with a simple analytical model and simulations.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356528","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Only in 4-gate SOI transistors (G/sup 4/-FETs) can the channel be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. The majority carriers flow in the film volume, far from interfaces and junctions. We show that inversion layers, formed at the front and back interface, enable the junction gates to have enhanced control on the volume channel. High performance is experimentally demonstrated in terms of transconductance, subthreshold swing and g/sub m//I/sub d/ ratio. The basic mechanism, which involves a specific 2D gate coupling, is explained with a simple analytical model and simulations.