Innovative practices session 9C: Yield improvement: Challenges and directions

Abstract

At the 32/28nm node and below, parametric and process marginality contribute increasing yield loss. Additionally, this yield loss is often asserted spatially. A further complication is that the interaction of design rules is increasing node over node, requiring ever more characterization and modeling. Thus, a significant increase in the quantity and quality of electrical characterization — including full wafer coverage — is necessary to rapidly diagnose, eliminate, and monitor these yield loss mechanisms. However, present test time budgets must be maintained. Our presentation focuses on methods to meet these requirements.