Effect of PCB stack-up on Temperature Cycling Reliability of WLCSP

R. Roucou, R. Rongen, J.J. M Zaal, P. van der Wel
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引用次数: 1

Abstract

This paper describes the use of a failure mechanism driven approach to develop and assess the reliability of new products during qualification. Due to their construction, Wafer Level Chip Scale Packages (WLCSP) have an increased interaction with the Printed Circuit Board (PCB) compared to more traditional packages. While mounted on the PCB, the thermo-mechanical stress during temperature cycling induces stress to the component via the solder joint. This stress can lead to cracks in the passivation layer, which propagates into the back end of line layers below and thus lead to an electrical failure of the component. On the one hand, the definition of the PCB (i.e. material and design) should mimic the stress from the final application (e.g. smart phone) and therefore be close to the application board. On the other hand, it must fulfill the requirements of the reliability stress testing by enabling the electrical testing of the component and surviving a larger stress as compared to the application.This study focusses on the effect of the PCB material (FR-4, FR-5 and Polyimide), its thickness (from 0.5mm to 1.6mm) and the number of copper layers in the PCB (from 4 layers to 10 layers). For these PCB variations, 6 configurations are defined and the components are subjected to temperature cycling stress testing. Based on the electrical failures due to cracks in the passivation, the effect of the stress is compared based on the statistical analysis of the failures rates. The 1.6mm PCB stack-ups with both polyimide and FR-4 are shown to induce more stress than the thinner PCBs. Due to its lower Young’s modulus compared to other materials, the thick FR-5 test carrier induces an equivalent stress compared to thinner FR-4 ones. The thinnest stack (0.5mm) being the least stressful for the passivation layer and the back end of line.In addition to the stress tests, finite element models are developed for a WLCSP mounted on various PCB configurations. Then, the thermo-mechanical stress is simulated and a good agreement is found with the performance ranking established from the application level temperature cycling test results. The outcome of this study enables the development of reliable components and the comparison of the stress during component qualification with the stress from its final assembly in the application.
PCB堆叠对WLCSP温度循环可靠性的影响
本文描述了在认证过程中使用失效机制驱动方法来开发和评估新产品的可靠性。由于其结构,与更传统的封装相比,晶圆级芯片规模封装(WLCSP)与印刷电路板(PCB)的交互作用增加。当安装在PCB上时,温度循环过程中的热机械应力通过焊点对组件产生应力。这种应力会导致钝化层中的裂纹,并传播到下面线路层的后端,从而导致组件的电气故障。一方面,PCB的定义(即材料和设计)应该模拟最终应用(例如智能手机)的应力,因此要接近应用板。另一方面,它必须满足可靠性压力测试的要求,通过使组件的电气测试和承受比应用程序更大的压力。本研究的重点是PCB材料(FR-4, FR-5和聚酰亚胺),其厚度(从0.5mm到1.6mm)和PCB中的铜层数(从4层到10层)的影响。对于这些PCB变化,定义了6种配置,并且组件要进行温度循环应力测试。以钝化过程中裂纹引起的电气失效为例,在对失效率进行统计分析的基础上,对应力的影响进行了比较。与较薄的PCB相比,含有聚酰亚胺和FR-4的1.6mm PCB堆叠显示出更大的应力。由于与其他材料相比,较厚的FR-5测试载体的杨氏模量较低,因此与较薄的FR-4测试载体相比,其产生的应力等效。最薄的堆叠(0.5mm)是钝化层和线后端的应力最小的。除了压力测试外,还为安装在各种PCB配置上的WLCSP开发了有限元模型。然后进行了热机械应力模拟,与应用级温度循环试验结果建立的性能排名吻合较好。这项研究的结果使可靠的组件的开发和应力的比较,在组件鉴定过程中,其最终装配在应用中的应力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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