Gate Impedance Analysis of SiC power MOSFETs with SiO2 and High-k Dielectric

Abstract

This paper shows how the gate impedance $Z_{\text{gg}}$ characterization of a SiC-power MOSFET can be used to investigate its dielectric-semiconductor interface quality distinguishing the channel and JFET contributions. The $Z_{\text{gg}}$ characterization is performed for SiC power MOSFETs with SiO2 and with high-k gate dielectrics. Different voltage- and temperature-dependencies of $Z_{\text{gg}}$ are identified in the respective SiC MOSFETs. The newer designs show an improvement with respect to the near semiconductor interface-traps. Experimental characterization and TCAD device simulations are carried out to support the conclusions.