Macro-modeling of transistor level receiver circuits

Abstract

A modeling methodology for macro-modeling transistor level receiver circuits has been proposed. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits i.e., the input characteristics of the receivers. In this work, the proposed modeling approach addresses both the loading effect of the receiver as well as the output characteristics of the receiver. The proposed modeling technique is simple, accurate and has huge computational speed-up over transistor level receiver circuits. A recurrent neural network (RNN) model is used to model the loading effect of the receiver. The output characteristics of the receiver is modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on a few test cases and results show good accuracy.