D. Dautriche, P. Lestrat, G. Josse, F. Debrie, G. Borel, E. Thouret
{"title":"0.8 /spl mu/m HSOI4CB rad-tolerant technology for space applications: a solution to harden existing components with minimum design risk","authors":"D. Dautriche, P. Lestrat, G. Josse, F. Debrie, G. Borel, E. Thouret","doi":"10.1109/RADECS.1995.509769","DOIUrl":null,"url":null,"abstract":"For several years, TCS has been involved in the transfer of epitaxial CMOS technology of microprocessors such as 68020 from Motorola and in the development of hardened Standard or ASIC products. The know-how which has bean acquired during these operations has led us to develop a rad tolerant process totally compatible in terms of design rules with standard CMOS process. Named HSOI4CB (CB for Compatible Bulk), this process is a 0.8 /spl mu/m SOI CMOS with 2 levels of metallization. The use of the HSOI4CB technology allows us, without any specific effort on the design, to reach hardening levels compatible with space requirements up to more than 100 Krads.","PeriodicalId":310087,"journal":{"name":"Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADECS.1995.509769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
For several years, TCS has been involved in the transfer of epitaxial CMOS technology of microprocessors such as 68020 from Motorola and in the development of hardened Standard or ASIC products. The know-how which has bean acquired during these operations has led us to develop a rad tolerant process totally compatible in terms of design rules with standard CMOS process. Named HSOI4CB (CB for Compatible Bulk), this process is a 0.8 /spl mu/m SOI CMOS with 2 levels of metallization. The use of the HSOI4CB technology allows us, without any specific effort on the design, to reach hardening levels compatible with space requirements up to more than 100 Krads.