Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis

Abstract

This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library, while preserving speed-independence. The algorithm exploits known efficient factorization techniques from combinational multi-level logic synthesis, but achieves also Boolean simplification. Experimental results show a significant improvement in terms of number and complexity of solvable circuits with respect to existing methods.