ASIC flow implementation over multi clock processor block on 32 nm Node

Abstract

Today as technology has reached up to 7nm, meeting timing constraints at such technology node has become very difficult. The experimentations have been done over a multi-clock processor block on 32 nm node where several algorithms for optimization techniques are used. The used algorithms include optimization features such as buffer sizing, gate sizing, delay insertion, buffer and gate relocation and dummy load insertion, setting of maximum fan-out variation, boundary timing optimization during concurrent clock and data and clock tree synthesis (CCD-CTS), scan chain optimization and power optimization. Each feature has its own algorithm and has gone through stages of improvement. These features are studied and implemented in both classic clock tree synthesis and concurrent clock and data CTS. Though selection of CTS style completely depends on the design complexity but it is observed that generally CCD style CTS gives better results. Complete analysis of CTS flow has been done including analysis of various new algorithms for better optimization and better QOR.