A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing

Abstract

This paper presents an power-efficient imprecise radix-4 multiplier applied to filtering Hi-Res (High Resolution) audio. The proposed multiplier was based on an imprecise 2×2 (m=2) multiplication block in order to implement optimized 2's complement radix-2m array multipliers. The imprecise 2×2 multiplication block was previously proposed in literature, and presents as main characteristic a tunable error that enables the building of an imprecise radix-4 multiplier with a reduced number of logic gates. Since in the radix-2m multiplier architecture the operands are split into groups of m bits, then, the m=2 imprecise multiplier is used as a basic component in its structure. Our work deals with different levels of approximation in the radix-2m multiplier. We present four different approximate radix-4 multipliers architectures to be used in sequential FIR filters implemented in hardware. The filters are described in VHDL and synthesized for ASIC in Cadence RTL Compiler tool using Nangate 45nm standard cells. The power reports are evaluated using real input vectors from Hi-Res audio sequences in order to obtain valid power dissipation results. The imprecise FIR filters present area and power reductions of up to 5.7% and 12.5% when compared to the precise designs without compromising the Signal to Noise Ratio (SNR) of recorded 24-bit@192kHz Hi-Res audio signals.