Low-power GPS receiver design

Abstract

This paper describes the design of a low-power global positioning system (GPS) receiver implemented in CMOS technology. The primary GPS ranging signal is broadcast at a frequency of 1.575 GHz, modulated by a pseudo-noise sequence at a chip rate of 1 MHz. The design of this low-power GPS receiver emphasizes the circuit techniques and architectural trade-offs employed in minimizing the energy needed for each position estimate.