Dynamic error correction technique for wide-band 0.4 – 4 GHz direct receiver

Abstract

This paper presents at high speed and wideband direct receiver based on delta-sigma architecture. The effects of inter-symbol inference are discussed in this paper. In addition, a robust technique using a Decision Feedback Equalizer for multi-level (three bits) non-return-to-zero feedback Digital-to-Analog Converter in the receiver is also studied. This technique is proposed to reduce the dynamic error effects on overall system Signal-to-Noise-and Distortion-Ratio, as well as compensate the non-idealities of the feedback Digital-to- Analog in multi-Gb/s data rate over high speed data conversion. The wide-band delta-sigma modulator architecture and the feedback Digital-to-Analog with Decision Feedback Equalizer are also presented in this paper. The simulation results confirm the advantages of the proposed system.