Perimeter effects from interfaces in ultra-thin layers deposited on nanometer-deep p+n silicon junctions

Abstract

Interface states at metal-semiconductor or semiconductor-semiconductor interfaces in ultra-thin layers deposited on nanometer-deep p+n silicon junctions that are contacted by metal, can be beneficial for suppressing the injection of majority carriers from the bulk. The effect is more pronounced as the p+n junction depth becomes smaller and it dominates the electrical characteristics of ultrashallow junctions, as, for example sub-10-nm deep pure boron (PureB) diodes. The properties of the perimeter of such an interface play a critical role in the overall electrical characteristics. In this paper, a TCAD simulation study is described where nanometer-deep p+n junctions have an interface hole-layer that forms an energy barrier at the semiconductor-semiconductor interface. The suppression of bulk electron injection is analyzed with respect to the barrier height and the p+n junction depth. Perimeter effects are investigated by 2D simulations showing a detrimental impact on the parasitic majority carrier injection from the bulk in structures with nanometer deep p+n junctions. Other than employing a guard ring, reduction of the perimeter effects by shifting the position of the metal electrode was considered.