Correctness of BDEC compared to PGM in assessing reliability of nano-based circuits

Abstract

As CMOS scales further into non-CMOS technology, being able to measure reliability of modern logic integrated circuits instantly and correctly is fast becoming necessary. Therefore, reliability assessment has become a decisive step in the design methodology of nano-sized circuit systems. In contemporary to current literature, the existing reliability assessment tool based on Probabilistic Gate Model (PGM) and Boolean Difference-error Calculator (BDEC) techniques works manually, thus making the process of computing reliability very intractable and time consuming. For an instant reliability measure, this paper firstly looks into the development of an automated reliability assessment tool based on the generalization of PGM and BDEC techniques. The Matlab-based tool allows users to speed-up the task of reliability analysis for large number of nano-based electronic circuits. Secondly, by using the developed automated tool, the work explores into the correctness of BDEC compared to PGM in assessing reliability of same functionality nano-based circuits. The reliability analysis shows that BDEC gives correct and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, BDEC tends to be more inferior in the reliability measure compared to PGM. The lower reliability measures by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC does not only depend on faulty gates but it also depends on circuit, probability of input signals being one or zero and probability of error on signal lines.