Improvement of Thermal Endurance for Integrated Millimeter-Wave Silicon IMPATT Device in µm2-Scale

Abstract

Based on the fact that the avalanche frequency of impact-ionization avalanche transit-time (IMPATT) diode is proportional to the square-root of DC biasing current density, more DC current injection is necessary to push the negative differential resistances (NDRs) into higher frequency regime. This leads to a serious thermal endurance problem for IMPATT devices in monolithic integration scenario, since the pn-junction area reaches only µm2-scale compared to traditional discrete cases of mm2-scale and on the other side there is lack of huge heat sink commonly applied in each discrete IMPATT component design. After characterizing series of fabricated IMPATT devices with pn-junction area of 30 × 2 µm2; 30 × 4 µm2; 30 × 6 µm2; 30 × 10 µm2, their avalanche frequencies haven been extracted and plotted over varied square-root of DC biasing current densities. The discrepancy between the estimated and measured profiles has confirmed and explained exactly the usually ignored temperature effect. Scanning electron microscopy (SEM) images have been taken for a burned out IMPATT diode of 30 × 2 µm2. The weak point did not occur at the expected “fragile” pn-junction, but at the metallic interconnect. This triggered an improvement of a new device layout design. The SEM images of two IMPATT diodes with the same pn-junction (30 × 2 µm2) but different layouts in the burn-out test verifies the improvement of device thermal endurance. Additionally, the IMp ATT diode with the new layout design offered 7 mA more regarding the maximum injected DC biasing current than the one with old layout design. This ensures the overall device robustness regarding thermal endurance for further circuit design.