Analog Spiking Neuron in 28 nm CMOS

Abstract

Traditional computer clusters are facing a significant limitation as a result of the big data revolution. We need efficient edge devices to bring the power of machine learning algorithms from power-hungry room servers to mobile consumer platforms. Neuromorphic engineering is a promising avenue for developing the next generation of edge devices that combine high computing capabilities with low power consumption in a small form factor. This paper shows the proof of concept of an analog/mixed-signal CMOS neuromorphic system on a chip (NeuroSoC) by presenting a low-power design of a leaky integrate-and-fire (LIF) neuron. The design uses eight transistors and two capacitors for low complexity and potential to lead to very dense systems. The proposed model consumes 1.2 fJ/spike and occupies an active area of 6.73 µm by 5.09 µm when implemented in 28 nm CMOS. The maximum spiking frequency is 343 kHz.